Memory Device Comprising an Electrically Floating Body Transistor and Methods of Using

ABSTRACT

A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.

CROSS-REFERENCE

This application claims the benefit of U.S. Provisional Application No. 62/415,511, filed Nov. 1, 2016, which application is hereby incorporated herein, in its entirety, by reference thereto.

This application claims the benefit of U.S. Provisional Application No. 62/451,439, filed Jan. 27, 2017, which application is hereby incorporated herein, in its entirety, by reference thereto.

This application claims the benefit of U.S. Provisional Application No. 62/461,160, filed Feb. 20, 2017, which application is hereby incorporated herein, in its entirety, by reference thereto.

This application claims the benefit of U.S. Provisional Application No. 62/552,048, filed Aug. 30, 2017, which application is hereby incorporated herein, in its entirety, by reference thereto.

FIELD OF THE INVENTION

The present invention relates to semiconductor memory technology. More specifically, the present invention relates to a semiconductor memory device comprising an electrically floating body transistor and an access transistor.

BACKGROUND OF THE INVENTION

Semiconductor memory devices are used extensively to store data. Memory devices can be characterized according to two general types: volatile and non-volatile. Volatile memory devices such as static random access memory (SRAM) and dynamic random access memory (DRAM) lose data that is stored therein when power is not continuously supplied thereto.

A DRAM cell without a capacitor has been investigated previously. Such memory eliminates the capacitor used in the conventional 1T/1C memory cell, and thus is easier to scale to smaller feature size. In addition, such memory allows for a smaller cell size compared to the conventional 1T/1C memory cell. Chatterjee et al. have proposed a Taper Isolated DRAM cell concept in “Taper Isolated Dynamic Gain RAM Cell”, P. K. Chatterjee et al., pp. 698-699, International Electron Devices Meeting, 1978 (“Chatterjee-1”), “Circuit Optimization of the Taper Isolated Dynamic Gain RAM Cell for VLSI Memories”, P. K. Chatterjee et al., pp. 22-23, IEEE International Solid-State Circuits Conference, February 1979 (“Chatterjee-2”), and “dRAM Design Using the Taper-Isolated Dynamic RAM Cell”, J. E. Leiss et al., pp. 337-344, IEEE Journal of Solid-State Circuits, vol. SC-17, no. 2, April 1982 (“Leiss”), all of which are hereby incorporated herein, in their entireties, by reference thereto. The holes are stored in a local potential minimum, which looks like a bowling alley, where a potential barrier for stored holes is provided. The channel region of the Taper Isolated DRAM cell contains a deep n-type implant and a shallow p-type implant. As shown in “A Survey of High-Density Dynamic RAM Cell Concepts”, P. K. Chatterjee et al., pp. 827-839, IEEE Transactions on Electron Devices, vol. ED-26, no. 6, June 1979 (“Chatterjee-3”), which is hereby incorporated herein, in its entirety, by reference thereto, the deep n-type implant isolates the shallow p-type implant and connects the n-type source and drain regions.

Terada et al. have proposed a Capacitance Coupling (CC) cell in “A New VLSI Memory Cell Using Capacitance Coupling (CC) Cell”, K. Terada et al., pp. 1319-1324, IEEE Transactions on Electron Devices, vol. ED-31, no. 9, September 1984 (“Terada”), while Erb has proposed Stratified Charge Memory in “Stratified Charge Memory”, D. M. Erb, pp. 24-25, IEEE International Solid-State Circuits Conference, February 1978 (“Erb”), both of which are hereby incorporated herein, in their entireties, by reference thereto.

DRAM based on the electrically floating body effect has been proposed both in silicon-on-insulator (SOI) substrate (see for example “The Multistable Charge-Controlled Memory Effect in SOI Transistors at Low Temperatures”, Tack et al., pp. 1373-1382, IEEE Transactions on Electron Devices, vol. 37, May 1990 (“Tack”), “A Capacitor-less 1T-DRAM Cell”, S. Okhonin et al., pp. 85-87, IEEE Electron Device Letters, vol. 23, no. 2, February 2002 and “Memory Design Using One-Transistor Gain Cell on SOI”, T. Ohsawa et al., pp. 152-153, Tech. Digest, 2002 IEEE International Solid-State Circuits Conference, February 2002, all of which are hereby incorporated herein, in their entireties, by reference thereto) and in bulk silicon (see for example “A one transistor cell on bulk substrate (1T-Bulk) for low-cost and high density eDRAM”, R. Ranica et al., pp. 128-129, Digest of Technical Papers, 2004 Symposium on VLSI Technology, June 2004 (“Ranica-1”), “Scaled 1T-Bulk Devices Built with CMOS 90 nm Technology for Low-Cost eDRAM Applications”, R. Ranica et al., 2005 Symposium on VLSI Technology, Digest of Technical Papers (“Ranica-2”), “Further Insight Into the Physics and Modeling of Floating-Body Capacitorless DRAMs”, A. Villaret et al, pp. 2447-2454, IEEE Transactions on Electron Devices, vol. 52, no. 11, November 2005 (“Villaret”), “Simulation of intrinsic bipolar transistor mechanisms for future capacitor-less eDRAM on bulk substrate”, R. Pulicani et al., pp. 966-969, 2010 17th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) (“Pulicani”), all of which are hereby incorporated herein, in their entireties, by reference thereto).

Widjaja and Or-Bach describe a bi-stable SRAM cell incorporating a floating body transistor, where more than one stable state exists for each memory cell (for example as described in U.S. Pat. No. 8,130,548 to Widjaja et al., titled “Semiconductor Memory Having Floating Body Transistor and Method of Operating” (“Widjaja-1”), U.S. Pat. No. 8,077,536, “Method of Operating Semiconductor Memory Device with Floating Body Transistor Using Silicon Controlled Rectifier Principle” (“Widjaja-2”), U.S. Pat. No. 9,230,651, “Memory Device Having Electrically Floating Body Transistor” (“Widjaja-3”), all of which are hereby incorporated herein, in their entireties, by reference thereto). This bi-stability is achieved due to the applied back bias which causes impact ionization and generates holes to compensate for the charge leakage current and recombination.

In a memory array comprising rows and columns of memory cells, performing an operation on a memory cell of the array may trigger a change in its surrounding memory cells, a condition often referred to as disturb. There is a continuing need for improving disturb resistance in memory cells. Two-transistor memory cells, for example as described in “Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI”, F. Morishita et al, Custom Integrated Circuits Conference, 2005, pp. 435-438, “A configurable enhanced TTRAM macro for system-level power management unified memory”, F. Morishita et al., Solid-State Circuits, IEEE Journal of, vol. 42 no. 4 (2007), pp. 853-861, “A high-density scalable twin transistor RAM (TTRAM) with verify control for SOI platform memory IPs”, K. Arimoto et al., Solid-State Circuits, IEEE Journal of, vol. 42, no. 11 (2007), pp. 2611-2619, and “A Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on SOI”, K. Arimoto et al. pp. 429-432, Custom Integrated Circuits Conference, 2006, U.S. patent application Ser. No. 14/380,779, “Memory Cell Comprising First and Second Transistors and Methods of Operating” (“Widjaja-4”), all of which are hereby incorporated herein, in their entireties, by reference thereto, may improve the disturb resistance of the memory cells.

SUMMARY OF THE INVENTION

A semiconductor memory cell comprising an electrically floating body transistor and an access transistor is disclosed. A method of operating the memory cell is disclosed.

According to one aspect of the present invention, a semiconductor memory cell is provided that includes: a memory transistor comprising a bi-stable floating body transistor having a first floating body region and a back-bias region configured to generate impact ionization when the memory cell is in one of first and second states, and wherein the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states; and an access device; wherein the access device comprises a second floating body region; and wherein the bi-stable floating body transistor and the access device are electrically connected in series.

In at least one embodiment, a capacitance of the first floating body region is different from a capacitance of the second floating body region.

In at least one embodiment, the memory transistor further comprises a first gate region, and the access device further comprises a second gate region.

In at least one embodiment, a length of the first gate region is less than a length of the second gate region.

In at least one embodiment, a length of the first gate region is greater than a length of the second gate region.

In at least one embodiment, a volume of the first floating body region is smaller than a volume of the second floating body region.

In at least one embodiment, a capacitance of the first gate region is different from a capacitance of the second gate region.

In at least one embodiment, at least one dummy gate region is provided between the memory transistor and the access device.

In at least one embodiment, the memory transistor comprises a first gate region; wherein a work function of the dummy gate region is higher than a work function of the first gate region.

In at least one embodiment, the semiconductor memory cell is a multi-port memory cell.

In at least one embodiment, the semiconductor memory cell comprises a fin structure.

According to another aspect of the present invention, a semiconductor memory cell includes: a first transistor having a first floating body; a second transistor having a second floating body; a buried layer underlying both of the first and second floating bodies; a first source line region contacting the first floating body; a first drain region separated from the first source line region and contacting the first floating body; a first gate insulated from the first floating body; an insulating member insulating the first floating body from the second floating body; a second source line region contacting the second floating body; a second drain region separated from the second source line region and contacting the second floating body; and a second gate insulated from the second floating body; wherein the first drain region is electrically connected to the second source line region; and wherein a capacitance of the first floating body is different from a capacitance of the second floating body.

In at least one embodiment, a volume of the first floating body is less than a volume of the second floating body.

In at least one embodiment, a length of the first gate is less than a length of the second gate.

In at least one embodiment, a length of the first gate is greater than a length of the second gate.

In at least one embodiment, the semiconductor memory cell further includes at least one dummy gate region between the first transistor and the second transistor.

In at least one embodiment, a work function of the dummy gate region is greater than a work function of the first gate.

In at least one embodiment, the first transistor and the second transistor have the same conductivity type.

In at least one embodiment, the semiconductor memory cell is a multi-port memory cell.

In at least one embodiment, the semiconductor memory cell includes a fin structure.

These and other advantages and features of the invention will become apparent to those persons skilled in the art upon reading the details of the memory cells, arrays and methods as more fully described below.

BRIEF DESCRIPTION OF THE DRAWINGS

In the course of the detailed description to follow, reference will be made to the attached drawings. These drawings show different aspects of the present invention and, where appropriate, reference numerals illustrating like structures, components, materials and/or elements in different figures are labeled similarly. It is understood that various combinations of the structures, components, materials and/or elements, other than those specifically shown, are contemplated and are within the scope of the present invention.

FIG. 1 is a block diagram for a memory instance.

FIG. 2 schematically illustrates a memory cell which comprises memory device and an access device that are connected in series.

FIGS. 3A and 3B are schematic, cross-sectional illustrations of a memory cell according to an embodiment of the present invention.

FIG. 4 schematically illustrates bias conditions applied to the memory cell of FIGS. 3A-3B during a holding operation.

FIG. 5 schematically illustrates a cross-sectional view of a memory cell according to another embodiment of the present invention.

FIG. 6 schematically illustrates a cross-sectional view of a memory cell according to another embodiment of the present invention.

FIG. 7 schematically illustrates a circuit representation of a memory array comprising memory cells illustrated in FIG. 5.

FIG. 8 is a cross-sectional, schematic illustration of a fin-type memory cell device according to an embodiment of the present invention.

FIGS. 9A, 9B, and 9C are schematic, layout views of a memory array according to an embodiment of the present invention.

FIG. 10 is a schematic, layout view of a memory array according to another embodiment of the present invention.

FIG. 11 is a schematic, layout view of a memory array according to another embodiment of the present invention.

FIG. 12 is a schematic, layout view of a memory array according to another embodiment of the present invention.

FIG. 13 is a schematic, cross-sectional view of a memory cell according to another embodiment of the present invention.

FIG. 14 is a schematic, cross-sectional view of a multi-port memory cell according to another embodiment of the present invention.

FIGS. 15A and 15B are schematic, layout views of a memory array comprising two rows and two columns of multi-port memory cells according to another embodiment of the present invention.

FIG. 16 is a schematic, cross-sectional view of two rows of multi-port memory cells illustrated in FIGS. 15A and 15B.

FIG. 17 is a schematic, cross-sectional view of a multi-port memory cell according to another embodiment of the present invention.

FIGS. 18 and 19 schematically illustrate cross-sectional views of variants of a memory cell according to an embodiment of the present invention.

FIG. 20A is a schematic, cross-sectional illustration of a memory cell according to another embodiment of the present invention.

FIG. 20B is a schematic, top-view illustration of the memory cell shown in

FIG. 20A.

FIGS. 21 and 22 are schematic, three-dimensional views of variants of a memory cell having a fin structure according to an embodiment of the present invention.

FIGS. 23-26 schematically illustrate layout views of a memory array according to another embodiment of the present invention.

FIG. 27 schematically illustrates a memory array of memory cells of the type shown in FIGS. 23-26 according to an embodiment of the present invention.

FIGS. 28A and 28B schematically illustrate layout views of a memory array according to another embodiment of the present invention.

FIG. 29 schematically illustrates a memory array of memory cells according to another embodiment of the present invention.

FIG. 30 schematically illustrates a read operation performed on a memory array according to an embodiment of the present invention.

FIG. 31 schematically illustrates a write logic-1 operation performed on a memory array according to an embodiment of the present invention.

FIGS. 32 and 33 schematically illustrate write logic-0 operations performed on a memory array according to an embodiment of the present invention.

FIGS. 34-37 schematically illustrate layout views of a memory array according to another embodiment of the present invention.

FIG. 38 schematically illustrates a memory array of memory cells according to another embodiment of the present invention.

FIG. 39 schematically illustrates a read operation performed on a memory array illustrated in FIG. 38 according to an embodiment of the present invention.

FIG. 40 schematically illustrates a write logic-1 operation performed on a memory array illustrated in FIG. 38 according to an embodiment of the present invention.

FIGS. 41-42 schematically illustrate write logic-0 operations performed on a memory array illustrated in FIG. 38 according to an embodiment of the present invention.

FIGS. 43A-48 schematically illustrate a memory array of memory cells having a memory transistor and an access transistor according to another embodiment of the present invention.

FIG. 49 schematically illustrates a memory array of dual-port memory cells according to another embodiment of the present invention.

FIGS. 50A-50B schematically illustrate a memory array after formation of a buried well and subsequent normal well, respectively, according to an embodiment of the present invention.

FIG. 51 schematically illustrates a memory array after formation of deep trench isolation along the word line direction according to an embodiment of the present invention.

FIG. 52 schematically illustrates a memory array after formation of shallow trench along the bit line direction according to an embodiment of the present invention.

FIG. 53 schematically illustrates a memory array after formation of recessed metal in the bottom region of the shallow trench according to an embodiment of the present invention.

FIG. 54 schematically illustrates a memory array after gap filling in the shallow trench according to an embodiment of the present invention.

FIG. 55 schematically illustrates a memory array after formation of gate stack and source and drain according to an embodiment of the present invention.

FIG. 56 is a cross-sectional illustration cut along the bit line direction of FIG. 55.

FIGS. 57A-57C are cross-sectional illustrations cut along the word line direction of FIG. 55.

FIG. 58 schematically illustrates a memory array according to another embodiment of the present invention.

FIG. 59 is a cross-sectional illustration cut along the bit line direction of FIG. 58.

FIG. 60 is a cross-sectional illustration cut along the word line direction of FIG. 58.

FIG. 61 schematically illustrates a layout view of a memory array according to another embodiment of the present invention.

FIG. 62 schematically illustrates a cross-sectional view of a memory cell according to another embodiment of the present invention.

FIG. 63 schematically illustrates a cross-sectional view of a memory cell comprising a fin structure according to another embodiment of the present invention.

FIG. 64 schematically illustrates a holding operation performed on a memory cell illustrated in FIG. 63 according to an embodiment of the present invention.

FIG. 65 schematically illustrates a read operation performed on a memory cell illustrated in FIG. 63 according to an embodiment of the present invention.

FIG. 66 schematically illustrates a write logic-1 operation performed on a memory cell illustrated in FIG. 63 according to an embodiment of the present invention.

FIG. 67 schematically illustrates a write logic-0 operation performed on a memory cell illustrated in FIG. 63 according to an embodiment of the present invention.

FIG. 68 schematically illustrates a cross-sectional view of a memory cell according to another embodiment of the present invention.

FIG. 69 schematically illustrates a cross-sectional view of a memory cell according to another embodiment of the present invention.

FIGS. 70A and 70B schematically illustrate cross-sectional views of a memory cell according to another embodiment of the present invention.

FIGS. 71A and 71B schematically illustrate cross-sectional views of a memory cell according to another embodiment of the present invention.

FIG. 72 schematically illustrates a cross-sectional view of a memory cell comprising an access transistor and a memory transistor having different conductivity type according to another embodiment of the present invention.

FIG. 73 schematically illustrates a write operation performed on a memory array comprising memory cells illustrated in FIG. 72 according to an embodiment of the present invention.

FIGS. 74A and 74B schematically illustrate write operations performed on a memory cell illustrated in FIG. 72, according to an embodiment of the present invention.

FIG. 75 schematically illustrates an exemplary waveform for a write operation performed on a memory cell illustrated in FIG. 72 according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Before the present memory cells, memory arrays and processes are described, it is to be understood that this invention is not limited to particular embodiments described, as such may, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting, since the scope of the present invention will be limited only by the appended claims.

Where a range of values is provided, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, between the upper and lower limits of that range is also specifically disclosed. Each smaller range between any stated value or intervening value in a stated range and any other stated or intervening value in that stated range is encompassed within the invention. The upper and lower limits of these smaller ranges may independently be included or excluded in the range, and each range where either, neither or both limits are included in the smaller ranges is also encompassed within the invention, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included in the invention.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Although any methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present invention, the preferred methods and materials are now described. All publications mentioned herein are incorporated herein by reference to disclose and describe the methods and/or materials in connection with which the publications are cited.

It must be noted that as used herein and in the appended claims, the singular forms “a”, “an”, and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a cell” includes a plurality of such cells and reference to “the bit line” includes reference to one or more bit lines and equivalents thereof known to those skilled in the art, and so forth.

The publications discussed herein are provided solely for their disclosure prior to the filing date of the present application. The dates of publication provided may be different from the actual publication dates which may need to be independently confirmed.

FIG. 1 illustrates a memory instance 1200, comprising memory array 100 and periphery circuitries associated with the memory array 100. Examples of the periphery circuitries are shown in FIG. 1: control logic 102 which receives for example enable (/E) and write (/W) signals and controls the operation of the memory array 100; address buffer 110, which transmits the address received to row decoder 112 and column decoder 114; reading circuitry such as sense amplifier 116 and error correction circuit (ECC) 118; data buffer 120, which outputs the read data or transmits the write data into write drivers 130; analog supply generators and/or regulator 140 which provides additional voltage levels needed for the memory array operation; redundancy logic 150 which may be used to increase the yield of the memory instance; built-in-self-test (BIST) 160 which may be used to set the trim levels for the supply generator 140 and/or replace the defective units with redundant array. The BIST may also sense the chip temperature and trim the voltage levels of the supply generator according to the temperature. The memory instance may be a discrete memory component or it may be embedded inside another integrated circuit device 1000.

Memory array 100 may comprise a plurality of memory cells 50, each of which comprises memory device 50M and access device 50A that are connected in series, as illustrated in FIG. 2. Memory cell 50 is a generic representation of a memory cell comprising a memory device and access device. Memory device 50M functions to store the state of the memory cell 50, and is accessed through the access device 50A. The access device 50A is connected to terminals, for example the word line terminal 72 and the bit line terminal 76 as shown in FIG. 2, which are used to select a memory cell 50 in a memory array 100 comprising a plurality of rows and columns of memory cells 50. In a series connection, such as in memory device 50M and access device 50A, the same current flows through each of the devices 50M and 50A. Therefore, the access device 50A can be used to turn-off or deselect an unselected memory cell 50 during read or write operations. A memory cell 50 comprising a floating body transistor as memory device 50M has been described for example in U.S. Patent Application Publication No. 2015/0023105, “Memory Cell Comprising First and Second Transistors and Method of Operating”, which is hereby incorporated herein, in its entirety, by reference thereto.

Referring to FIG. 3A, a memory cell 502 according an embodiment of the present invention is shown. Memory device 502 comprises two transistors: transistor 502M having an electrically floating body 24 and access transistor 502A. Memory cell 502 includes a substrate 10 of a first conductivity type such as p-type, for example. Substrate 10 is typically made of silicon, but may also comprise, for example, germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials. In some embodiments of the invention, substrate 10 can be the bulk material of the semiconductor wafer. In other embodiments, substrate 10 can be a well of the first conductivity type embedded in either a well of the second conductivity type or, alternatively, in the bulk of the semiconductor wafer of the second conductivity type, such as n-type, for example, (not shown in the figures) as a matter of design choice. To simplify the description, the substrate 10 will usually be drawn as the semiconductor bulk material as it is in FIG. 3A.

Memory cell 502 also comprises a buried layer region 30 of a second conductivity type, such as n-type, for example; a floating body region 24 of the first conductivity type, such as p-type, for example; and source/drain regions 16 and 18 of the second conductivity type, such as n-type, for example. Buried layer 30 may be formed by an ion implantation process on the material of substrate 10. Alternatively, buried layer 30 can be grown epitaxially on top of substrate 10.

The floating body region 24 of the memory transistor 502M having a first conductivity type is bounded on top by surface 14, source line region 16, drain region 18, and insulating layer 62, on the sides by insulating layer 26, and on the bottom by buried layer 30, while the floating body region 24 of the access transistor 502A is bounded on top by surface 14, source region 20, bit line region 22, and insulating layer 66, on the sides by insulating layer 26, and on the bottom by buried layer 30. Floating body 24 may be the portion of the original substrate 10 above buried layer 30 if buried layer 30 is implanted. Alternatively, floating body 24 may be epitaxially grown. Depending on how buried layer 30 and floating body 24 are formed, floating body 24 may have the same doping as substrate 10 in some embodiments or a different doping, if desired in other embodiments.

A gate 60 of the memory transistor 502M is positioned in between the source line region 16 and the drain region 18, above the floating body region 24. The gate 60 is insulated from the floating body region 24 by an insulating layer 62. Insulating layer 62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The gate 60 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.

A gate 64 of the access transistor 502A is positioned in between the source region 20 and the bit line region 22. The gate 64 is insulated from the floating body region 24 by an insulating layer 66. Insulating layer 66 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The gate 64 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.

Insulating layers 26 (like, for example, shallow trench isolation (STI)), may be made of silicon oxide, for example, though other insulating materials may be used. Insulating layers 26 insulate floating body transistor 40 from adjacent floating body transistor 40 and adjacent access transistor 42. The bottom of insulating layer 26 may reside inside the buried region 30 allowing buried region 30 to be continuous as shown in FIG. 3A. Alternatively, the bottom of insulating layer 26 may reside below the buried region 30. This requires a shallower insulating layer 28, which insulates the floating body region 24, but allows the buried layer 30 to be continuous in the perpendicular direction of the cross-sectional view shown in FIG. 3A (for example, see the insulating layer 26 and the shallower insulating layer 28 in FIG. 20A, which allows for buried layer 22 (FIG. 20A) to be continuous in the perpendicular direction of the cross-sectional view shown in FIGS. 3A and 20A, but discontinuous to adjacent memory cells in the “same plane” as the cross-sectional view shown in FIGS. 3A and 20A). For simplicity, only memory cell 502 with continuous buried region 30 in all directions will be shown from hereon.

The drain region 18 of the memory transistor 502M is connected to the source region 20 of the access transistor 502A through a conductive element 96, 94 a, 94 b. Conductive element 90 connects the source line region 16 of the memory transistor 502M (which may be referred to as the source line region 16 of the memory device 502 interchangeably) to the source line (SL) terminal 74, while conductive element 92 connects the bit line region 22 of the access transistor 502A (which may be referred to as the bit line region 22 of the memory device 502 interchangeably) to the bit line (BL) terminal 76. The conductive elements 90, 92, 96, 94 a, 94 b may be formed of, but not limited to, cobalt, tungsten or silicided silicon.

In addition to the SL terminal 74 and BL terminal 76, memory cell 502 also includes word line 1 (WL1) terminal 70, which is electrically connected to the gate 60 of the memory transistor 502M, word line 2 (WL2) terminal 72, which is electrically connected to the gate 64 of the access transistor 502A, buried well (BW) terminal 78, which is electrically connected to the buried well region 30 of the floating body transistor 502M, and substrate (SUB) terminal 80, which is connected to the substrate region 10.

The memory cell 502 comprises memory transistor 502M and access transistor 502A having the same conductivity type. For example, both memory transistor 502M and access transistor 502A may be n-channel transistors. The access transistor 502A may have different gate and gate insulating layer stacks from the memory transistor 502M such that the capacitive coupling from the gate region 64 to the floating body region 24 of the access transistor 502A is lower than that of the memory transistor 502M. For example, the gate 64 of the access transistor may be made of different materials from the gate 60 of the memory transistor. Similarly the gate insulating layer 66 of the access transistor may be made of different materials or may have different thickness from the gate insulating layer 62.

In an alternative embodiment shown in FIG. 3B, the drain region 18 of the memory device 502M and the source region 20 of the access device 502A may be connected through a conductive element 94.

Several operations can be performed to memory cell 502, such as: holding, read, write logic-1 and write logic-0 operations and have been described, for example, in Widjaja-4.

During the operation of memory cell 502, to prevent a positive charge accumulation in the floating body region 24 of access transistor 502A, a negative voltage may be applied to the bit line region 22. A negative voltage may also be applied to the gate region 64 of the access transistor 502A, to prevent the negative voltage applied to the bit line region 22 to propagate to the memory transistor 502M. The level of the negative voltage applied to the bit line region 22 may be decided to conditionally remove the positive charges only when the floating body is positively charged but not cause to flow a forward biased junction current when the floating body is neutrally charged. Such voltage may range from −0.05V to −0.6V.

FIG. 4 illustrates exemplary bias conditions for the holding operation of the memory cell 502: about 0.0 volts is applied to WL1 terminal 70, about −0.2 volts is applied to WL2 terminal 72, about 0.0 volts is applied to SL terminal 74, about −0.2 volts is applied to BL terminal 76, about 0.0 volts is applied to SUB terminal 78, and a positive voltage like, for example, +1.2 volts is applied to BW terminal 78. In other embodiments, different voltages may be applied to the various terminals of memory cell 502 as a matter of design choice and the exemplary voltages described are not limiting in any way.

FIG. 5 illustrates memory cell 504 according to another embodiment of the present invention. Memory cell 504 comprises memory transistor 504M and access transistor 504A having different volumes of floating body regions 24 relative to one another. Therefore, the floating body capacitance of the floating body regions 24 will be different. The access transistor 504A of the memory cell 504 is illustrated having a larger floating body region 24 than floating body region 24 of memory cell 504 (and longer gate region 64 than the length of gate region 60). Depending on the capacitive coupling of the gate region 64 to the floating body region 24, capacitive coupling of the bit line region 22 to the floating body region 24, the capacitive coupling of the source region 20 to the floating body region, and the capacitive coupling from the buried well region 30 to the floating body region 24 compared to the corresponding capacitive coupling of the memory transistor 504M, the access transistor 504A may have a smaller floating body region 24 (and shorter gate region 64 than the length of gate region 60).

FIG. 6 illustrates memory cell 506 according to another embodiment of the present invention. The bit line region 22 is shared between adjacent access transistors 506A. An exemplary memory array 1506 comprising memory cells 506 is shown in FIG. 7, illustrating bit line region 22 (connected to BL terminals 76 (i.e., 76 a, 76 b, . . . , 76 p) is shared between adjacent memory cells 506. As a result, the floating body region 24 of the access transistor 506A is now larger than the floating body region 24 of the memory transistor 506M while the gate length of the access transistor 506A and the memory transistor 506M is identical.

Memory cells 502, 504, and 506 may also comprise a fin structure. FIG. 8 schematically illustrates a three-dimensional memory cell 502F comprising a fin structure 52.

FIGS. 9A and 9B illustrate exemplary layout views of a memory array 1502 comprising a plurality of rows and columns of memory cells 502, where both memory device 502M and access device 502A are of the same conductivity type, for example where both memory device 502M and access device 502A are n-channel transistors. The memory device 502M is formed by the DIFF 130, POLY 160, and BNWL layers 170, while the access device 502A is formed by the DIFF 130 and POLY 160 layers. Also illustrated in FIG. 9A is CONT 140 and MTL1 180, which forms the series connection between memory device 502M and access device 502A.

Referring to the layout view shown in FIG. 9A and the cross-sectional view shown in FIG. 3A, the active regions of the memory device 502M, which comprise floating body region 24, source line region 16, drain region 18, are defined by the DIFF layer 130. The insulating layer 26 is defined by the space between the DIFF layers 130. The gate region 60 is defined by the POLY layer 160, while the buried layer 30 is defined by the BNWL layer 170. The buried layer 30 is designed such that when a back bias is applied to the buried layer 30, impact ionization is generated when the memory device 502M is in logic-1 state, but no impact ionization is generated when the memory device 502M is in logic-0 state, for example as described in U.S. Pat. No. 9,230,651, “Memory Device Having Electrically Floating Body Transistor”, which is hereby incorporated herein, in its entirety, by reference thereto.

Referring to the layout view shown in FIG. 9A and the cross-sectional view shown in FIG. 3A, the active regions of the access device 502A, which comprise floating body region 24, source region 20, bit line region 22, are defined by the DIFF layer 130. The insulating layer 26 is defined by the space between the DIFF layers 130. The gate region 64 is defined by the POLY layer 160.

In another embodiment illustrated in the layout view in FIG. 9C, the buried layer 30 (defined by BNWL layer 170) is only formed underneath the memory device 502M. The well region of the access device 502A is connected to the substrate region 12.

Conductive element 90 connects the source line region 16 of the memory device 502M (which may be referred to as the source line region 16 of the memory device 502 interchangeably) to the source line (SL) terminal 74 (through another conductive element similar to conductive element 96 defined by layer MTL1 180, shown separately in FIG. 9B for clarity), while conductive element 92 connects the bit line region 22 of the access device 502A (which may be referred to as the bit line region 22 of the memory device 502 interchangeably) to the bit line (BL) terminal 76 (through another conductive element similar to conductive element 96 defined by MTL1 layer 180, which is then connected to MTL2 layer 182 through a conductive element similar to conductive elements 90, 92, 94 a, and 94 b defined by VIA1 layer 142, shown separately in FIG. 9B for clarity). The conductive elements 90, 92, 94 a, and 94 b may be formed of, but not limited to, tungsten or silicided silicon.

Referring to both the layout view shown in FIGS. 9A and 9B and the cross-sectional view shown in FIG. 3A, the conductive elements 90, 92, 94 a, and 94 b are defined by CONT 140, and the conductive element 96 is defined by MTL1 layer 180.

For a three-dimensional memory cell structure, for example memory cell 502F comprising a fin structure 52 extending substantially perpendicular to, and above the top surface of the substrate 10, the fin 52 as shown in FIG. 8, is defined by DIFF layer 30 in FIGS. 9A-9C.

FIG. 10 shows a layout view of memory array 1508 according to another embodiment of the present invention. Relative to the memory array 1502 of FIGS. 9A-9B, memory array 1508 includes an additional dummy POLY layer 160D which does not overlay a DIFF region 130 (hence being referred to as dummy layer). The dummy layer 160D for example may be a result of restrictive design rules (which guides the layout drawing of the layers) for better lithography patterning process. As shown in FIG. 10, the unit cell of the memory cell 502 comprises three POLY 160 regions, one 160D to define the dummy region and two 160 to define the transistor regions (overlapping with DIFF layer 130, where one defines the memory device 502M and the other defines the access device 502A). Depending on the process technology node, more than one dummy POLY layer 160D may be used.

Memory cell 502 is used as an illustrative example to describe the layout view in FIG. 10. The use of dummy POLY layer 160D may also be used for memory cells 504, 506, 502F, 504F, and 506F.

FIG. 11 illustrates a schematic layout view of memory array 1510 according to another embodiment of the present invention where the DIFF layers 130 are arranged in a staggered or zig-zag pattern. As a result, memory device 502M and access device 502A in adjacent columns do not share the same POLY layer 160. In the example illustrated in FIG. 11, the memory devices 502M are positioned in the left column, while the access devices 502A are positioned in the right column. In the exemplary array shown in FIG. 11, the buried well region 30 (defined by the BNWL layer 170) is only formed underneath the memory devices 502M. In FIG. 11, the first POLY layer 160 (from the top) defines the gate region 64 of an access device 502A in the right column shown and the second POLY layer 160 (from the top) defines the gate region 60 of a memory device 502M in the left column shown. Subsequently, the third POLY layer 160 defines another gate region 64 of another access device 502A.

Memory cell 502 is used as an illustrative example to describe the layout view in FIG. 11. The arrangement of DIFF layers 130 in a staggered or zig-zag pattern may also be used for memory cells 504, 506, 502F, 504F, and 506F. Furthermore, the buried well region 30 (defined by the BNWL layer 170) may also be formed underneath both memory device 502M and access device 502A.

FIGS. 12 and 13 illustrate schematic layout and cross-sectional views of memory array 1512 comprising a plurality of rows and columns of memory cells 512 according to another embodiment of the present invention, where the memory device 512M and access device 512A′ have different conductivity type. For example, memory device 512M is an n-channel transistor, while access device 512A′ is a p-channel transistor. The memory device 512M comprises a floating body region 24 having a first conductivity type, such as p-type. Access transistor 512A′ comprises a well region 12′ of the second conductivity type, such as n-type, source region 20′ and bit line region 22′ of the first conductivity type, such as p-type. The well region 12′ of the second conductivity type is electrically connected to the buried well region 30, and is therefore not floating.

Referring to the layout view shown in FIG. 12, the BNWL layer 170 encloses both memory device 512M and access device 512A′, as the buried layer 30 is formed underneath both memory device 512M and access device 512A′. The well region 12′ of the access device 512A′ is defined by the layer 190. Similarly, the source region 20′ and bit line region 22′ of the access device 512A′ are defined using a different layer from the source line region 16 and drain region 18 of the memory device 512M.

Memory array 1512 may be implemented in three-dimensional structure similar to what is shown in FIG. 8. Memory array 1512 may also require dummy POLY layers as shown in FIG. 10. The arrangement of DIFF layers 130 in a zig-zag pattern illustrated in FIG. 11 may also be applied to memory array 1512.

FIG. 14 illustrates a schematic cross-sectional view of a multi-port memory cell 310 according to another embodiment of the present invention. Memory cell 310 comprises a bi-stable floating body transistor 310M having a floating body region 124 having a first conductivity type, for example p-type. A buried layer region 122 having a second conductivity type, for example n-type, is formed underneath the floating body region 124. The buried layer 122 is designed such that when a back bias is applied to the buried layer 122, impact ionization is generated when the memory device 310 is in logic-1 state, but no impact ionization is generated when the memory device 310 is in logic-0 state, for example as described in U.S. Pat. No. 9,230,651, “Memory Device Having Electrically Floating Body Transistor”, which is hereby incorporated herein, in its entirety, by reference thereto.

The bi-stable floating body transistor 310M also comprises regions 116, 118, and 120 having a second conductivity type, and gate regions 160 and 162 insulated from the floating body region 124 by insulating layers 130 and 132, respectively.

Memory cell 310 also comprises an access transistor 310A having a well region 112 having a second conductivity type, for example n-type, regions 117 and 119 having a first conductivity type, for example p-type, and a gate region 164 insulated from the well region 112 by an insulating layer 134. The region 119 of the access transistor is connected to the region 120 of the bi-stable floating body transistor 120 through a conductive element 94, forming a series connection between the access transistor 310A and the bi-stable floating body transistor 310M.

Memory cell 310 includes word line #1 (WL1) terminal 190 electrically connected to gate 160, word line #2 (WL2) terminal 192 electrically connected to gate 162, a source line (SL) terminal 172 electrically connected to region 116, a bit line #1 (BL1) terminal 174 electrically connected to region 118, a select gate #2 (SG2) terminal 194 electrically connected to gate 164, bit line #2 (BL2) terminal 176 electrically connected to region 117, buried well (BW) terminal 178 electrically connected to the buried layer 122, and substrate (SUB) terminal 170 electrically connected to the substrate region 110. WL1 terminal 190 and BL1 terminal 174 may be referred to herein as ‘port #1’, while WL2 terminal 192, SG2 terminal 194, and BL2 terminal 176 may be referred to herein as ‘port #2’.

Several operations can be performed to memory cell 310, such as: holding, read, write logic-1 and write logic-0 operations. The read and write operations can be performed on memory cell 310 through port #1 and port #2.

The holding operation of the bi-stable floating body transistor has been described for example as described in U.S. Pat. No. 8,130,548 to Widjaja et al., titled “Semiconductor Memory Having Floating Body Transistor and Method of Operating” (“Widjaja-1”), U.S. Pat. No. 8,077,536, “Method of Operating Semiconductor Memory Device with Floating Body Transistor Using Silicon Controlled Rectifier Principle” (“Widjaja-2”), U.S. Pat. No. 9,230,651, “Memory Device Having Electrically Floating Body Transistor” (“Widjaja-3”), all of which are hereby incorporated herein, in their entireties, by reference thereto. The holding operation may be performed by applying a positive bias to the BW terminal 178, zero or negative bias on the WL1 terminal 190, WL2 terminal 192, a positive bias to the SG2 terminal 194, about zero potential on the BL1 terminal 174, BL2 terminal 176, SL terminal 172, and substrate terminal 78.

In one embodiment the bias conditions for the holding operation for memory cell 310 are: 0.0 volts is applied to WL1 terminal 190, 0.0 volts is applied to WL2 terminal 192, +1.2 volts is applied to SG2 terminal 194, about 0.0 volts is applied to the SL terminal 172, BL1 terminal 174, BL2 terminal 176, and SUB terminal 170, and a positive voltage like, for example, +1.2 volts is applied to BW terminal 178. In other embodiments, different voltages may be applied to the various terminals of memory cell 310 as a matter of design choice and the exemplary voltages described are not limiting in any way.

The read and write operations of memory cell 310 through port #1 have also been described in Widjaja-1, Widjaja-2, and Widjaja-3.

A read operation may be performed through port #1 for example by applying the following bias conditions: a positive voltage is applied to the BW terminal 178, zero voltage is applied to SL terminal 172, a positive voltage is applied to the selected BL1 terminal 174, and a positive voltage greater than the positive voltage applied to the selected BL1 terminal 174 is applied to the selected WL1 terminal 190, and zero voltage is applied to the SUB terminal 170. The unselected BL1 terminals will remain at zero voltage and the unselected WL1 terminals will remain at zero or negative voltage.

In one particular non-limiting embodiment, about 0.0 volts is applied to SL terminal 172, about +0.4 volts is applied to the selected BL1 terminal 174, about +1.2 volts is applied to the selected WL1 terminal 190, about +1.2 volts is applied to BW terminal 178, and about 0.0 volts is applied to the SUB terminal. The unselected BL1 terminals 174 remain at 0.0 volts and the unselected WL1 terminals 190 remain at 0.0 volts. However, these voltage levels may vary.

A write “0” operation of the memory cell 310 may be performed by applying the following bias conditions: a negative bias is applied to SL terminal 172, zero or negative voltage is applied to WL1 terminal 190, and zero or positive voltage is applied to BW terminal 178, and zero voltage is applied to the BL1 terminal 174 and SUB terminal 170. The SL terminal 172 for the unselected cells will remain grounded. Under these conditions, the p-n junction between 124 and 116 is forward-biased, evacuating any holes from the floating body 124.

In one particular non-limiting embodiment, about −0.5 volts is applied to SL terminal 172, about −0.5 volts is applied to WL1 terminal 190, about 0.0 volts is applied to the BL1 terminal 174, and about +1.2 volts is applied to terminal 178. However, these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above.

An alternative write “0” operation that allows for individual bit writing may be performed by applying a positive voltage to WL1 terminal 190, a negative voltage to BL1 terminal 174, zero or positive voltage to SL terminal 172, and zero or positive voltage to BW terminal 178, and zero voltage to SUB terminal 170. Under these conditions, the floating body 124 potential will increase through capacitive coupling from the positive voltage applied to the WL1 terminal 190. As a result of the floating body 124 potential increase and the negative voltage applied to the BL1 terminal 174, the p-n junction between 124 and 118 is forward-biased, evacuating any holes from the floating body 124. To reduce undesired write “0” disturb to other memory cells 310 in a memory array, the applied potential can be optimized as follows: if the floating body 124 potential of state “1” is referred to as V_(FB1), then the voltage applied to the WL1 terminal 190 is configured to increase the floating body 124 potential by V_(FB1)/2 while −V_(FB1)/2 is applied to BL1 terminal 174. A positive voltage can be applied to SL terminal 172 to further reduce the undesired write “0” disturb on other memory cells 310 in a memory array. The unselected cells will remain at holding state, i.e. zero or negative voltage applied to WL1 terminal 190 and zero voltage applied to BL1 terminal 174.

In one particular non-limiting embodiment, the following bias conditions are applied to the selected memory cell 310: a potential of about 0.0 volts is applied to SL terminal 172, a potential of about −0.2 volts is applied to BL1 terminal 174, a potential of about +1.2 volts is applied to WL1 terminal 190, about +1.2 volts is applied to BW terminal 178, and about 0.0 volts is applied to SUB terminal 170; while about 0.0 volts is applied to SL terminal 172, about 0.0 volts is applied to BL1 terminal 174, about 0.0 volts is applied to WL1 terminal 190, and about +1.2 volts is applied to BW terminal 178 of the unselected memory cells. However, these voltage levels may vary.

A write “1” operation may be performed by applying a positive voltage to WL1 terminal 190, a positive voltage to BL1 terminal 174, zero or positive voltage to SL terminal 172, and zero or positive voltage to BW terminal 178, and zero voltage to SUB terminal 170.

In one particular non-limiting embodiment, the following bias conditions are applied to the selected memory cell 310: a potential of about 0.0 volts is applied to SL terminal 172, a potential of about +1.2 volts is applied to BL1 terminal 174, a potential of about +1.2 volts is applied to WL1 terminal 190, about +1.2 volts is applied to BW terminal 178, and about 0.0 volts is applied to SUB terminal 170; while about 0.0 volts is applied to SL terminal 172, about 0.0 volts is applied to BL1 terminal 174, about 0.0 volts is applied to WL1 terminal 190, and about +1.2 volts is applied to BW terminal 178 of the unselected memory cells. However, these voltage levels may vary.

Read and write operations through port #2 can be performed by first turning on the access transistor connected in series with the bi-stable floating body transistor, for example as described in U.S. Patent Application Publication No. 2015/0023105, “Memory Cell Comprising First and Second Transistors and Method of Operating”, which is hereby incorporated herein, in its entirety, by reference thereto.

A read operation may be performed through port #2 for example by applying the following bias conditions: a positive voltage is applied to the BW terminal 178, zero voltage is applied to SL terminal 172, a positive voltage is applied to the selected BL2 terminal 176, and zero or a positive voltage is applied to the selected WL2 terminal 192, and zero voltage is applied to the SUB terminal 170. For p-type transistor illustrated in FIG. 14, the access transistor is turned on by applying zero or negative voltage to the selected SG2 terminal 194. The unselected BL2 terminals will remain at zero voltage and the unselected WL2 terminals will remain at zero or negative voltage, while the unselected access transistors will remain off by applying a positive voltage to the unselected SG2 terminals.

In one particular non-limiting embodiment, about 0.0 volts is applied to SL terminal 172, about +0.4 volts is applied to the selected BL2 terminal 176, about 0.0 volts is applied to the selected WL2 terminal 192, about −0.5 volts is applied to SG2 terminal 194, about +1.2 volts is applied to BW terminal 178, and about 0.0 volts is applied to the SUB terminal. The unselected BL2 terminals 176 remain at 0.0 volts, the unselected WL2 terminals 192 remain at 0.0 volts, and the unselected SG2 terminals 194 remain at about +1.2 volts. However, these voltage levels may vary.

A write “0” operation may be performed through port #2 for example by applying the following bias conditions: a positive voltage is applied to the BW terminal 178, zero voltage is applied to SL terminal 172, a negative voltage is applied to the selected BL2 terminal 176, and a positive voltage is applied to the selected WL2 terminal 192, and zero voltage is applied to the SUB terminal 170. For p-type transistor illustrated in FIG. 14, the access transistor is turned on by applying zero or negative voltage to the selected SG2 terminal 194. The unselected BL2 terminals will remain at zero voltage and the unselected WL2 terminals will remain at zero or negative voltage, while the unselected access transistors will remain off by applying a positive voltage to the unselected SG2 terminals.

In one particular non-limiting embodiment, about 0.0 volts is applied to SL terminal 172, about −0.2 volts is applied to the selected BL2 terminal 176, about +1.2 volts is applied to the selected WL2 terminal 192, about −0.5 volts is applied to SG2 terminal 194, about +1.2 volts is applied to BW terminal 178, and about 0.0 volts is applied to the SUB terminal. The unselected BL2 terminals 176 remain at 0.0 volts, the unselected WL2 terminals 192 remain at 0.0 volts, and the unselected SG2 terminals 194 remain at about +1.2 volts. However, these voltage levels may vary.

A write “1” operation may be performed through port #2 for example by applying the following bias conditions: a positive voltage is applied to the BW terminal 178, zero voltage is applied to SL terminal 172, a positive voltage is applied to the selected BL2 terminal 176, a positive voltage is applied to the selected WL2 terminal 192, and zero voltage is applied to the SUB terminal 170. For p-type transistor illustrated in FIG. 14, the access transistor is turned on by applying zero or negative voltage to the selected SG2 terminal 194. The unselected BL2 terminals will remain at zero voltage and the unselected WL2 terminals will remain at zero or negative voltage, while the unselected access transistors will remain off by applying a positive voltage to the unselected SG2 terminals.

In one particular non-limiting embodiment, about 0.0 volts is applied to SL terminal 172, about +1.2 volts is applied to the selected BL2 terminal 176, about +1.2 volts is applied to the selected WL2 terminal 192, about −0.5 volts is applied to SG2 terminal 194, about +1.2 volts is applied to BW terminal 178, and about 0.0 volts is applied to the SUB terminal. The unselected BL2 terminals 176 remain at 0.0 volts, the unselected WL2 terminals 192 remain at 0.0 volts, while the unselected SG2 terminals 194 remain at about +1.2 volts. However, these voltage levels may vary.

From the foregoing it can be seen that memory cell 310 may function as a multi-port memory cell. Port #1 and port #2 can both be used as read and access port. It may also be configured, for example, such that port #1 is used only for read operation and port #2 is used for both read and write operations.

FIGS. 15A, 15B, and 16 illustrate schematic layout and cross-sectional views of a memory array comprising two rows and two columns of memory cells 310, where adjacent memory cells 310 are mirrored to share the contact or via to the region 117 (see FIG. 16), connecting it to the BL2 terminal 176. For simplicity, not all the layers are shown in FIGS. 15A, 15B, and 16.

Referring to the layout views shown in FIGS. 15A and 15B, the active regions of the bi-stable floating body transistor and access transistor are defined by the DIFF layer 130, while the spaces between the DIFF layer 130 define the insulating layers 126. The gate regions are defined by the POLY layers 160, 162, and 164, while layer 180 defines a metal layer MTL1. The WL1 terminal 190 a, WL2 terminal 192 a, SG2 terminal 194 a, along with SL1 terminal 172 a define a row of memory cells 310, while WL1 terminal 190 b, WL2 terminal 192 b, SG2 terminal 194 b, and the SL1 terminal 172 b define another row of memory cells 310.

FIG. 15B shows the connections to the MTL2 layer 182, which form electrical connections to the BL1 terminal 174 and BL2 terminal 176. The BL1 terminal 174 a and BL2 terminal 176 a define a column of memory cells 310, while BL1 terminal 174 b and BL2 terminal 176 b define another column of memory cells 310. The MTL2 layer 182 is connected to the MTL1 layer 180 through a via layer 142.

FIG. 17 illustrates a schematic cross-sectional view of a multi-port memory cell 320 according to another embodiment of the present invention, where both bi-stable floating body transistor and access transistor have the same conductivity type, for example n-type transistors.

Multi-port memory cells 310 and 320 may also be implemented in three-dimensional structure similar to what is shown in FIG. 8. A memory array comprising a plurality of multi-port memory cells 310 and 320 may also require dummy POLY layers as shown in FIG. 10. The arrangement of DIFF layers 130 in a zig-zag pattern illustrated in FIG. 11 may also be applied to memory arrays comprising a plurality of multi-port memory cells 310 or 320.

A memory array of the present invention may comprise a plurality of memory cells 520 according to another embodiment of the present invention. FIG. 18 is a schematic, cross-sectional illustration of memory cell 520. Memory cell 520 may function as a memory device 50M illustrated in FIG. 2. Memory cell 520 includes a substrate 12 of a first conductivity type such as p-type, for example. Substrate 12 is typically made of silicon, but may also comprise, for example, germanium, silicon germanium, gallium arsenide, carbon nanotubes, and/or other semiconductor materials. In some embodiments of the invention, substrate 12 can be the bulk material of the semiconductor wafer. In another embodiment shown in FIG. 19, substrate 12A of a first conductivity type (for example, p-type) can be a well of the first conductivity type embedded in a well 29 of the second conductivity type, such as n-type. The well 29 in turn can be another well inside substrate 12B of the first conductivity type (for example, p-type). In another embodiment, well 12A can be embedded inside the bulk of the semiconductor wafer of the second conductivity type (for example, n-type). These arrangements allow for segmentation of the substrate terminal, which is connected to region 12A. To simplify the description, the substrate 12 will usually be drawn as the semiconductor bulk material as it is in FIG. 18.

Memory cell 520 also includes a buried layer region 22 of a second conductivity type, such as n-type, for example; a floating body region 24 of the first conductivity type, such as p-type, for example; and source/drain regions 16 and 18 of the second conductivity type, such as n-type, for example.

Buried layer 22 may be formed by an ion implantation process on the material of substrate 12. Alternatively, buried layer 22 can be grown epitaxially on top of substrate 12 or formed through a solid state diffusion process.

The floating body region 24 of the first conductivity type is bounded on top by source line region 16, drain region 18, and insulating layer 62 (or by surface 14 in general), on the sides by insulating layer 26, and on the bottom by buried layer 22. Floating body 24 may be the portion of the original substrate 12 above buried layer 22 if buried layer 22 is implanted. Alternatively, floating body 24 may be epitaxially grown. Depending on how buried layer 22 and floating body 24 are formed, floating body 24 may have the same doping as substrate 12 in some embodiments or a different doping, if desired in other embodiments.

A source line region 16 having a second conductivity type, such as n-type, for example, is provided in floating body region 24, so as to bound a portion of the top of the floating body region in a manner discussed above, and is exposed at surface 14. Source line region 16 may be formed by an implantation process on the material making up substrate 12, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion or a selective epitaxial growth process could be used to form source line region 16.

A bit line region 18, also referred to as drain region 18, having a second conductivity type, such as n-type, for example, is also provided in floating body region 24, so as to bound a portion of the top of the floating body region in a manner discussed above, and is exposed at cell surface 14. Bit line region 18 may be formed by an implantation process on the material making up substrate 12, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion or a selective epitaxial growth process could be used to form bit line region 18.

A gate 60 is positioned in between the source line region 16 and the drain region 18, above the floating body region 24. The gate 60 is insulated from the floating body region 24 by an insulating layer 62. Insulating layer 62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The gate 60 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.

Insulating layers 26 (like, for example, shallow trench isolation (STI)), may be made of silicon oxide, for example, though other insulating materials may be used. Insulating layers 26 insulate memory cell 50 from adjacent memory cell 50. The bottom of insulating layer 26 may reside inside the buried region 22 allowing buried region 22 to be continuous as shown in FIGS. 18 and 19. Alternatively, the bottom of insulating layer 26 may reside below the buried region 22 as in FIGS. 20A and 20B (shown better in FIG. 20A). This requires a shallower insulating layer 28, which insulates the floating body region 24, but allows the buried layer 22 to be continuous in the perpendicular direction of the cross-sectional view shown in FIG. 20A. For simplicity, only memory cell 520 with continuous buried region 22 in all directions will be shown from hereon.

Cell 520 includes several terminals: word line (WL) terminal 70 electrically connected to gate 60, bit line (BL) terminal 74 electrically connected to bit line region 18, source line (SL) terminal 72 electrically connected to source line region 16, buried well (BW) terminal 76 electrically connected to buried layer 22, and substrate terminal 78 electrically connected to the substrate 12. Alternatively, the SL terminal 72 may be electrically connected to region 18 and BL terminal 74 may be electrically connected to region 16.

FIGS. 21 and 22 illustrate a schematic three-dimensional views of memory cell 520F having a fin structure according to another embodiment of the present invention. Memory cell 520F has a fin structure 52 fabricated on substrate 12 of a first conductivity type such as p-type for example, so as to extend from the surface of the substrate to form a three-dimensional structure, with fin 52 extending substantially perpendicular to and above the top surface of the substrate 12. Fin structure 52 is semiconductive and is built on buried well layer 22 of a second conductivity type such as n-type for example, which is itself built on top of substrate 12. Alternatively, buried well 22 could be a diffusion region inside substrate 12 with the rest of the fin 52 constructed above it, or buried well 22 could be a conductive layer on top of substrate 12 connected to all the other fin 52 structures in a manner similar to memory cell 520 described above. Fin 52 is typically made of silicon, but may comprise germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials known in the art. In other embodiments, substrate 12A can be a well of the first conductivity type embedded in either a well 29 of the second conductivity type or, alternatively, in the bulk of the semiconductor wafer of the second conductivity type, such as n-type, for example as shown in FIG. 22. To simplify the description, the substrate 12 will usually be drawn as the semiconductor bulk material as it is in FIG. 21.

FIG. 23 illustrates a layout view of memory array 1520 according to another embodiment of the present invention. The memory array 1520 is located within a buried well region 170 layer. The memory array 1520 includes additional dummy POLY layers 160D which only partially overlay a DIFF region 130 (hence being referred to as dummy layer). The dummy layer 160D for example may be a result of restrictive design rules (which guides the layout drawing of the layers) for better lithography patterning process. The DIFF layers 130 define the active regions of the memory cell (regions between the insulating layers shown in the cross-sectional view in FIG. 20A), where the layers in between the DIFF layers 130 define the insulating layers 26. The POLY layers 160 and dummy POLY layers 160D define the gate region 60 shown in the cross-sectional view of FIG. 20A.

As shown in FIG. 23, the unit cell of the memory cell 520 comprises three POLY 160 regions: two 160D to define the dummy region and another 160 to define the transistor region (fully overlapping with DIFF layer 130). The overlap between POLY 160 and DIFF 130 layers form the channel region of the memory cell 520, for example the region beneath gate region 60 and dielectric layer 62, between the source line region 16 and bit line region 18 shown in FIG. 18.

FIG. 24 illustrates a layout view of memory array 1520, illustrating examples on how electrical contact to the source line region 16 and bit line region 18 are formed. In the exemplary layout view shown in FIG. 24, two different CONT layers are shown: CONT-A 140A which is used to form connection to the DIFF region 130, and CONT-B 140B which is used to form between DIFF region 130 and the dummy POLY layer 160D. The dummy POLY layers 160D are cut into shorter lines (for example, compared to the dummy POLY layers 160D shown in FIG. 23) to prevent electrical shorts between adjacent memory cells 520 connected through CONT-B 140B layers. The dummy POLY 160D layers could be cut using a POLYCUT layer perpendicular to POLY direction, for example, to etch a continuous dummy POLY 160D layer.

FIG. 25 illustrates the conductive METAL1 150 layers, for example metal layers which connect the different regions of the memory cells 520 through the CONT layers. In the example illustrated in FIG. 25, a METAL1 150 layer connects source line regions 16 of adjacent memory cells 520 through CONT-A layers 140A (which may then be connected to a SL terminal 72), and bit line regions 18 of two neighboring memory cells 50 through CONT-A 140A and CONT-B 140B layers. The bit line regions 18 connected by METAL1 150 layer may then be connected by a METAL2 layers 152 to BL terminals 74, for example as shown in FIG. 26.

FIG. 27 schematically illustrates an exemplary embodiment of a memory array 1520 of memory cells 520 (four exemplary instances of memory cell 520 being labeled as 520 a, 520 b, 520 c and 520 d) arranged in rows and columns. In many, but not necessarily all, of the figures where memory array appears, representative memory cell 520 a will be representative of a “selected” memory cell 520 when the operation being described has one (or more in some embodiments) selected memory cell(s) 520. In such figures, representative memory cell 520 b will be representative of an unselected memory cell 520 sharing the same row as selected representative memory cell 520 a, representative memory cell 520 c will be representative of an unselected memory cell 520 sharing the same column as selected representative memory cell 520 a, and representative memory cell 520 d will be representative of an unselected memory cell 520 sharing neither a row or a column with selected representative memory cell 520 a.

FIGS. 28A and 28B illustrate an exemplary memory array 1530 of memory cells 530 according to another embodiment of the present invention. CONT-A layers 140A are used to connect two neighboring source line regions 16 and two neighboring bit line regions 18 of adjacent memory cells 530 in an alternating pattern, such that only one of the two memory cells connected by one CONT-A layer 140A is the same as the two memory cells connected by another CONT-A layer 140A. Conductive METAL layers 152 are then used to connect the source line regions 16 and bit line regions 18 of the memory cells to the BL terminals 74.

FIG. 29 illustrates an exemplary embodiment of the memory array 1530, where each BL terminal 74 is shared by adjacent memory cells 530, connecting the source line regions 16 or bit line regions 18 of adjacent memory cells 530.

Several operations can be performed by memory cell 530 such as holding, read, write logic-1 and write logic-0 operations, and have been described in U.S. Pat. No. 9,230,651 to Widjaja et al., titled “Memory Device Having Floating Body Transistor” (“Widjaja-3”) and U.S. Pat. No. 8,077,536, “Method of Operating Semiconductor Memory Device with Floating Body Transistor Using Silicon Controlled Rectifier Principle” (“Widjaja-2”), which are both hereby incorporated herein, in their entireties, by reference thereto.

FIG. 30 illustrates a read operation performed on memory array 1530. A read operation is performed by applying a positive bias on the selected WL terminal 70, applying a positive bias to the first selected BL terminal 74 b (less positive than the positive bias applied to the selected WL terminal 70), zero bias to the second selected BL terminal 74 a, a positive bias applied to the BW terminal 76, and zero bias applied to the substrate terminal 78.

In the shared BL architecture of memory array 1530 shown in FIG. 29, applying a positive voltage to the selected BL terminal 74 will result in current flow through two adjacent memory cells 530 if the adjacent BL terminals 74 (adjacent to the selected BL terminal 74) are grounded (or at a lower bias than the selected BL terminal 74). In order to ensure that the current only flows through the selected memory cell 530, the same positive bias could be applied to the BL terminal adjacent to the selected BL terminal. In the exemplary read operation shown in FIG. 30, a positive bias is applied to the BL terminals 74 b and 74 c. As a result, electrical current will only flow through the memory cells 530 a (between BL terminals 74 b and 74 a) and 530 b (between BL terminals 74 c and 74 d). In this manner, two memory cells 530 a and 530 b can simultaneously be read if desired.

In one embodiment the bias conditions for the read operation on memory cell 530 are: +1.0 volts is applied to selected WL terminal 70, 0 V is applied to unselected WL terminal 70, +0.2 volts is applied to the first selected BL terminals 74 (BL terminals 74 b and 74 c in FIG. 30) and 0 volts to the second selected BL terminals (BL terminals 74 a and 74 d in FIG. 30), 0 volts is applied to unselected BL terminal 74, a positive voltage, for example, +1.0 volts is applied to BW terminal 76, and 0 volts is applied to the substrate terminal 78. In other embodiments, different voltages may be applied to the various terminals of memory cell 530 and the exemplary voltages described are not limiting.

FIG. 31 illustrates an example of a write logic-1 operation performed on memory array 1530. The write logic-1 operation can be performed through capacitive coupling from the gate 60, source line region 16, and bit line region 18 to the floating body region 24. The operating region for the write logic-1 operation has been described for example in U.S. application Ser. No. 14/825,268, “Memory Device Comprising of an Electrically Floating Body Transistor” (“Han”), which is hereby incorporated herein, in its entirety, by reference thereto.

In the shared BL architecture of memory 1530 shown in FIG. 29, applying a pulse of positive voltage specified in Han to the selected BL terminal 74 will result in writing two adjacent memory cells. Therefore, as shown in FIG. 31, a pulse of lower positive voltage (for example Vdd/2, where Vdd is the operating voltage) is applied to both selected BL terminals 74 b and 74 c connected to the selected memory cell.

In one embodiment the bias conditions for the write logic-1 operation on memory cell 530 are: +1.0 volts is applied to selected WL terminal 70, 0 V is applied to unselected WL terminal 70, +0.5 volts is applied to the selected BL terminals 74 (BL terminals 74 b and 74 c connected to the selected cell 530 a in FIG. 31), 0 volts is applied to unselected BL terminal 74, a positive voltage, for example, +1.0 volts is applied to BW terminal 76, and 0 volts is applied to the substrate terminal 78. In other embodiments, different voltages may be applied to the various terminals of memory cell 530 and the exemplary voltages described are not limiting.

Applying +0.5 volts to the selected BL terminals 74 will avoid writing to the adjacent memory cells 530 sharing the same BL terminal 74 (for example compared to applying +1.0 volts to both WL terminal 70 and BL terminals 74). The selected memory cell 530 will receive capacitive coupling from both source line region 16 and bit line region 18 connected to the selected BL terminals 74 (e.g. BL terminals 74 b and 74 c in FIG. 31).

FIG. 32 illustrates an example of a write logic-0 operation performed on memory array 1530. The write logic-0 operation can be performed through forward biasing the p-n junction between floating body region 24 and source line region 16 and bit line region 18 and assisted by capacitive coupling from the gate 60 to the floating body region 24. The operating region for the write logic-0 operation has been described for example in U.S. application Ser. No. 14/825,268, “Memory Device Comprising of an Electrically Floating Body Transistor” (“Han”), which is hereby incorporated herein, in its entirety, by reference thereto.

In the shared BL architecture of memory 1530 shown in FIG. 29, applying a negative voltage specified in Han to the selected BL terminal 74 will result in writing two adjacent memory cells. Therefore, as shown in FIG. 32, a lower positive voltage (for example −Vdd/4, where Vdd is the operating voltage) is applied to both selected BL terminals 74 (BL terminals 74 b and 74 c in FIG. 32) connected to the selected memory cell 530 a.

In one embodiment the bias conditions for the write logic-0 operation on memory cell 530 are: +1.0 volts is applied to selected WL terminal 70, 0 V is applied to unselected WL terminal 70, −0.3 volts is applied to the selected BL terminals 74 (BL terminals 74 b and 74 c connected to the selected cell 530 a in FIG. 32), 0 volts is applied to unselected BL terminal 74, a positive voltage, for example, +1.0 volts is applied to BW terminal 76, and 0 volts is applied to the substrate terminal 78. In other embodiments, different voltages may be applied to the various terminals of memory cell 530 and the exemplary voltages described are not limiting.

Applying −0.3 volts to the selected BL terminals 74 will avoid writing logic-0 to the adjacent memory cells 530 sharing the same BL terminal 74 (for example compared to applying −0.5 volts to both BL terminals 74). The charge stored in selected memory cell 530 will be evacuated through forward-biasing both source line region 16 and bit line region 18 connected to the selected BL terminals 74 (e.g. BL terminals 74 b and 74 c in FIG. 32).

FIG. 33 illustrates an example of a write logic-0 performed on memory array 1530 according to another embodiment of the present invention. The write logic-0 is performed by forward biasing the p-n junction between floating body region 24 and source line region 16 and bit line region 18, and will write logic-0 to all the memory cells in one column connected to both selected BL terminals 74 (the columns located between BL terminals 74 b and 74 c in FIG. 33).

In one embodiment the bias conditions for the write logic-0 operation on memory cell 530 are: 0 volts is applied to WL terminal 70, −0.6 volts is applied to the selected BL terminals 74, 0 volts is applied to unselected BL terminals 74, a positive voltage, for example, +1.0 volts is applied to BW terminal 76, and 0 volts is applied to the substrate terminal 78. In other embodiments, different voltages may be applied to the various terminals of memory cell 530 and the exemplary voltages described are not limiting.

If desired, write logic-0 can be performed on three columns simultaneously. For example, by applying −1.0 volts to BL terminals 74 b and 74 c, three columns of memory cells (the first 3 left columns in FIG. 33) will be simultaneously written to logic-0 state.

FIGS. 34-37 illustrate a memory array 1540 of memory cells 540 according to another embodiment of the present invention. As shown in FIG. 35, the CONT layers connect two source line regions 16 and two bit line regions 18 of adjacent memory cells 540 in an alternating pattern. The source line regions 16 of two memory cells in adjacent rows are connected through conducting METAL layers 152, but all bit line regions 18 of an adjacent row are connected through conducting METAL layer 152. The source line regions are then connected to other conducting METAL layers 154 through a VIA layer 153 alternatingly as shown in FIGS. 36-37, resulting in a memory array architecture illustrated in FIG. 38. The memory array architecture 1540 results in a single memory cell 540 being selected through a combination of WL terminal 70 (connected to the gate region defined by POLY layer 160), BL terminal 74, and SL terminal 72.

FIG. 39 illustrates an example of a read operation performed on memory array 1540. A read operation is performed by applying a positive bias on the selected WL terminal 70, applying a positive bias to the selected BL terminal 74 (less positive than the positive bias applied to the selected WL terminal 70), zero voltage to the selected SL terminal 72, a positive bias applied to the BW terminal 76, and zero bias applied to the substrate terminal 78.

In the shared BL architecture of memory 1540 shown in FIG. 38, applying a positive voltage to the selected BL terminal 74 will result in current flow through two adjacent memory cells 540 if both of the SL terminals 72 are grounded (or at a lower bias than the selected BL terminal 74). In order to ensure that the current only flows through the selected memory cell 540, the same positive bias as applied to the selected BL terminal could be applied to the unselected SL terminal 72 adjacent to the selected memory cell 540. In the exemplary read operation shown in FIG. 39, a positive bias is applied to the unselected SL terminal 72 b. As a result, electrical current will only flow through the memory cell 540 a.

FIG. 40 illustrates an example of a write logic-1 operation performed on memory array 1540. The write logic-1 operation can be performed through capacitive coupling from the gate 60, source line region 16, and bit line region 18 to the floating body region 24. In the shared BL architecture of memory 1540 shown in FIG. 38, applying a positive voltage pulse specified in Han to the selected BL terminal 74 will result in writing two adjacent memory cells. Therefore, as shown in FIG. 40, a lower positive voltage (for example Vdd/2, where Vdd is the operating voltage) is applied to both selected BL terminal 74 and selected SL terminal 72 connected to the selected memory cell.

In one embodiment the bias conditions for the write logic-1 operation on memory cell 540 are: +1.0 volts is applied to selected WL terminal 70, 0 volt is applied to unselected WL terminal 70, +0.5 volts is applied to the selected BL terminal 74, +0.5 volts is applied to the selected SL terminal 72, a positive voltage, for example, +1.0 volts is applied to BW terminal 76, and 0 volts is applied to the substrate terminal 78. In other embodiments, different voltages may be applied to the various terminals of memory cell 540 and the exemplary voltages described are not limiting.

Applying +0.5 volts to the selected BL terminals 74 will avoid writing to the adjacent memory cells 540 sharing the same BL terminal 74 (for example compared to applying +1.0 volts to both WL terminal 70 and BL terminals 74). The selected memory cell 540 will receive capacitive coupling from both source line region 16 and bit line region 18 connected to the selected BL terminals 74 (e.g. BL terminal 74 a and SL terminal 72 a in FIG. 40).

FIG. 41 illustrates an example of a write logic-0 operation performed on memory array 1540. The write logic-0 operation can be performed through forward biasing the p-n junction between floating body region 24 and source line region 16 and bit line region 18 and assisted by capacitive coupling from the gate 60 to the floating body region 24. In the shared BL architecture of memory 1540 shown in FIG. 38, applying a negative voltage specified in Han to the selected BL terminal 74 will result in writing two adjacent memory cells. Therefore, as shown in FIG. 41, a lower negative voltage (for example −Vdd/4, where Vdd is the operating voltage) is applied to both selected BL terminal 74 and SL terminal 72 connected to the selected memory cell.

In one embodiment the bias conditions for the write logic-0 operation on memory cell 540 are: +1.0 volts is applied to selected WL terminal 70, 0 volts is applied to unselected WL terminal 70, −0.3 volts is applied to the selected BL terminal 74, −0.3 volts is applied to selected SL terminal 74, a positive voltage, for example, +1.0 volts is applied to BW terminal 76, and 0 volts is applied to the substrate terminal 78. In other embodiments, different voltages may be applied to the various terminals of memory cell 540 and the exemplary voltages described are not limiting.

Applying −0.3 volts to the selected BL terminal 74 and selected SL terminal 72 will avoid writing to the adjacent memory cells 540 sharing the same BL terminal 74 (for example compared to applying −0.5 volts to the selected BL terminal 74). The charge stored in selected memory cell 540 will be evacuated through forward-biasing both source line region 16 and bit line region 18 connected to the selected BL terminal 74 and SL terminal 72 (e.g. BL terminal 74 a and SL terminal 72 a in FIG. 41).

FIG. 42 illustrates an example of a write logic-0 operation performed on memory array 1540 according to another embodiment of the present invention. The write logic-0 is performed by forward biasing the p-n junction between floating body region 24 and source line region 16, and will write logic-0 to all the memory cells connected to the selected SL terminal 72.

In one embodiment the bias conditions for the write logic-0 operation on memory cell 540 are: 0 volts is applied to WL terminal 70, −1.0 volts is applied to the selected SL terminal 72, 0 volts is applied to all BL terminals 74, a positive voltage, for example, +1.0 volts is applied to BW terminal 76, and 0 volts is applied to the substrate terminal 78. In other embodiments, different voltages may be applied to the various terminals of memory cell 540 and the exemplary voltages described are not limiting.

If desired, write logic-0 can be performed on two rows simultaneously. For example, by applying −1.0 volts to SL terminals 72 a and 72 b as shown in FIG. 42, resulting in two rows of memory cells being simultaneously written to logic-0 state.

FIGS. 43A-46 illustrate a memory array 1550, comprising memory cells 550 according to an embodiment of the present invention. Memory cell 550 comprises memory device 550M and access device 550A, which are connected in series, and has been described for example in U.S. application Ser. No. 14/380,779, “Memory Cell Comprising First and Second Transistors and Methods of Operating” (“Widjaja-4”), which is hereby incorporated herein, in its entirety, by reference thereto. The memory devices 550M are transistors found inside the buried layer 170 while the access devices 550A are transistors located outside of the buried layer 170.

As illustrated in FIG. 43A, CONT-A 140A layer can be used to form a connection to the DIFF region 130 to the conductive element, for example METAL1 layers 150 shown in FIG. 44, and CONT-B 140B can be used to form a connection between DIFF region 130 and the dummy POLY layer 160D. The dummy POLY layers 160D are cut into shorter lines (for example, compared to the dummy POLY layers 160D shown in FIG. 34) to prevent electrical shorts between adjacent memory cells 550 connected through CONT-B 140B layers. The dummy POLY 160D layers could be cut using a POLYCUT layer, for example, to etch a continuous dummy POLY 160D layer. The CONT-A 140A and CONT-B 140B layers may also be placed alternatingly such as illustrated for example in FIG. 43B.

FIG. 44 illustrates the conductive METAL1 layers, for example metal layers, 150 which connect the different regions of the memory cells 50 through the CONT layers. In the example illustrated in FIG. 44, a METAL1 layer 150 connects source line regions 16 of adjacent memory cells 550 through CONT-A layers 140A (which may then be connected to a SL terminal 72). The METAL1 layer 150 also connects the drain region 18 of the memory cell 550M to the source region 20 of the access device 550A. The bit line region 22 of the access device 550A can then be connected to another conductive layer (for example METAL2 layer 152) through a VIA layer 153 as shown in FIGS. 45-46.

The exemplary memory cell 550 illustrated in FIGS. 43A-46 comprises two transistors (550M and 550A) having the same conductivity type, for example two n-channel transistors connected in series, where the memory transistor 550M is located within a buried well region 170 layer.

FIG. 47A illustrates a memory array 1550′ according to another embodiment of the present invention, where the memory transistor 550M and the access transistor 550A′ of memory cell 550′ are comprised of transistors having different conductivity type. The access transistor 550A′ may be p-channel transistor whereas the memory transistor 550M may be n-channel transistor. The access transistor 550A′ is located within a well region 170′ having a different type of the well region than that of the memory transistor 550M. The bit line metal and source line metal are subsequently formed according to the same manner explained in FIGS. 44-46. The CONT-A 140A and CONT-B 140B layers may also be drawn alternatingly such as illustrated for example in FIG. 47B.

FIG. 48 illustrates a memory array 1650 according to another embodiment of the present invention, where memory cell 650 comprises a memory transistor 650M and an access transistor 650A. As illustrated in FIG. 48, the DIFF layers 130 are arranged in a staggered or zig-zag pattern. The memory transistor 650M is located within a buried well region, which is defined by the buried well layer 170. The buried well region may also be formed through a self-aligned process, during the formation step of the active region and insulator region 26. The memory array 1650 may also be formed by memory cell 650′ having transistors of different conductivity type.

FIG. 49 illustrates a memory array 1660 according another embodiment of the present invention, comprising multi-port memory cells 660, which have been described for example in U.S. Pat. No. 8,582,359, “Dual-Port Semiconductor Memory and FIFO Memory Having Electrically Floating Body Transistor” (“Widjaja-5”), which is hereby incorporated herein, in its entirety, by reference thereto. CONT-A 140A layer can be used to form connection to the DIFF region 130 to a conductive element, for example METAL layers, and CONT-B 140B can be used to form a connection between DIFF region 130 and the dummy POLY layer 160D. The dummy POLY layers 160D are cut into shorter lines (for example, compared to the dummy POLY layers 160D shown in FIG. 34) to prevent electrical shorts between adjacent memory cells 660 connected through CONT-B 140B layers. The dummy POLY 160D layers could be cut using a POLYCUT layer, for example, to etch a continuous dummy POLY 160D layer.

The memory cell 660 illustrated in FIG. 49 is a dual-port memory cell where region 20, source line region 16 and the gate region in between (formed by the POLY 160 layer) form the first port, where region 18, source line region 16 and the gate region in between (formed by the POLY 160 layer) form the second port. The dual-port memory cell 660 can be extended into multi-port memory cells as described in Widjaja-5.

Referring to FIG. 50A, a process step for the buried well and subsequent well formation according to an embodiment of the present invention is shown. The process includes providing a substrate 12 of a first conductivity type such as p-type, for example. Alternatively, the first conductivity type can be n-type. Substrate 12 is typically made of silicon, but may also comprise, for example, germanium, silicon germanium, gallium arsenide, carbon nanotubes, and/or other semiconductor materials. In some embodiments of the invention, substrate 12 can be the bulk material of the semiconductor wafer. In another embodiment shown in FIG. 50B, substrate 12A of a first conductivity type (for example, p-type) can be a well of the first conductivity type embedded in a well 29 of the second conductivity type, such as n-type. The well 29 in turn can be another well inside substrate 12B of the first conductivity type (for example, p-type). In another embodiment, well 12A can be embedded inside the bulk of the semiconductor wafer of the second conductivity type (for example, n-type), where region 29 represents bulk semiconductor substrate having second conductivity type. To simplify the description, the substrate 12 will usually be drawn as the semiconductor bulk material as it is in FIG. 50A.

After this process step, device also includes a buried layer region 22 of a second conductivity type, such as n-type, for example (or p-type, when the first conductivity type is n-type); a well region 24 of the first conductivity type, such as p-type, for example. Some portion of the well region 24 will be floating body region of memory device when the process is completed.

Buried layer region 22 may be formed by an ion implantation process on the material of substrate 12. Alternatively, buried layer region 22 and the well region 24 can be grown epitaxially on top of substrate 12 or formed through a solid state diffusion process.

FIG. 51 is a schematic illustration after completing the deep trench isolation 26 process. Using a well-known etch mask (not shown) process such as pad oxide and silicon nitride mask, the well region 24 and the buried layer 22 are etched. The deep trench etching extends down through the upper surface of the substrate 12. Then, the deep trenches are filled with insulating material such as silicon dioxide, followed by chemical mechanical polishing to planarize the surface. The deep trench oxides 26 are parallel to each other along the word line direction to be formed.

FIG. 52 is a schematic illustration after completing the shallow trench 27 etch process. Using a well-known etch mask (not shown) process such as pad oxide and silicon nitride mask, the well region 24 and the buried layer 22 are etched perpendicular to the deep trench isolation 26. These shallow trench 27 etchings may be completed when the bottom surfaces reside inside the buried layer 22 or, alternatively, the etchings can be extended down through the buried layer 22 but not substantially below the upper surface of the substrate 12. To simplify the description, the shallow trench 27 will be drawn as the bottom surface residing slightly below the upper surface of the substrate 12. The shallow trenches 27 are parallel to each other along the bit line direction to be formed.

FIG. 53 is a schematic illustration after completing the recessed metal 40 formation process. Using a well-known etch mask (not shown) process such as pad oxide and silicon nitride mask, the shallow trench 27 is filled with a metal and etched back. The upper surface of the recessed metal 40 is made to reside below the upper surface of the buried layer 22, so that the recessed metal connects the adjacent buried layers 22 but not the well 24 regions. Therefore, the buried layer 22 can be electrically continuous through chain connection through the recessed metals 40 along the word line direction.

FIG. 54 is a schematic illustration after completing the shallow trench isolation 28 process. The shallow trenches 27 are filled with insulating material such as silicon dioxide, followed by chemical mechanical polishing to planarize the surface.

FIG. 55 is a schematic illustration after completing the gate stack 60, 62, source region 16, and drain region 18 formations. The lines shown indicate the word line and bit line directions.

FIG. 56 illustrates a cross-sectional illustration cut along the bit line direction of FIG. 55. Referring to the memory cell 520, the floating body region 24 of the first conductivity type is bounded on top by source line region 16, drain region 18, and insulating layer 62 (or by surface 14 in general), on the sides perpendicular to the bit line direction by deep trench isolation 26, on the other sides perpendicular to the word line direction by shallow trench isolation 28 (see FIG. 57), and on the bottom by buried layer 22. The bottom of the deep trench isolation 26 resides below the interface between the buried layer 22 and the substrate 12, which insulates the floating body region 24 as well as the buried layer 22 along the bit line direction.

Floating body 24 may be the portion of the original substrate 12 above buried layer 22 if buried layer 22 is implanted. Alternatively, floating body 24 may be epitaxially grown. Depending on how buried layer 22 and floating body 24 are formed, floating body 24 may have the same doping as substrate 12 in some embodiments or a different doping, if desired in other embodiments.

A source line region 16, also referred to as source region 16, having a second conductivity type, such as n-type, for example (or p-type, when the first conductivity type is n-type), is provided in floating body region 24, so as to bound a portion of the top of the floating body region in a manner discussed above, and is exposed at surface 14. Source line region 16 may be formed by an implantation process on the material making up substrate 12, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion or a selective epitaxial growth process could be used to form source line region 16.

A bit line region 18, also referred to as drain region 18, having a second conductivity type, such as n-type, for example (or p-type, when the first conductivity type is n-type), is also provided in floating body region 24, so as to bound a portion of the top of the floating body region in a manner discussed above, and is exposed at cell surface 14. Bit line region 18 may be formed by an implantation process on the material making up substrate 12, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion or a selective epitaxial growth process could be used to form bit line region 18.

A gate 60 is positioned in between the source line region 16 and the drain region 18, above the floating body region 24. The gate 60 is insulated from the floating body region 24 by an insulating layer 62. Insulating layer 62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The gate 60 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.

Cell 520 includes several terminals: word line (WL) terminal 70 electrically connected to gate 60, bit line (BL) terminal 74 electrically connected to bit line region 18, source line (SL) terminal 72 electrically connected to source line region 16, buried well (BW) or deep n-well (DNWL) terminal 76 electrically connected to buried layer 22, and substrate terminal 78 electrically connected to the substrate 12. Alternatively, the SL terminal 72 may be electrically connected to region 18 and BL terminal 74 may be electrically connected to region 16.

FIGS. 57A-57C illustrate cross-sectional illustrations cut along the word line direction of FIG. 55. FIG. 57A illustrates a cross-sectional illustration of an embodiment of the present invention. The recessed metal 40 connects the neighboring buried layers 22 along the word line direction, but not along the bit line direction due to deep trench isolation 26. FIG. 57B illustrates a cross-sectional illustration of another embodiment of the present invention. The buffer oxide 41 may be present at the bottom of the shallow trench so that the bottom of the recessed metal 40 may not directly touch the substrate 12 while connecting the neighboring buried layers 22. FIG. 57C illustrates a cross-sectional illustration of another embodiment of the present invention. The bottom of the shallow trench isolation 28 resides inside the buried layer 22. Therefore, the recessed metal 40 is made in parallel to the buried layer 22. The buried layer 22 becomes continuous along the word line direction while its resistivity may be enhanced by the periodically placed, recessed metals. Note that the recessed metals 40 are not made to contact to the floating body 24 or the substrate 12.

Referring to FIG. 58, a memory device 750 according to another embodiment of the present invention is shown. FIG. 59 and FIG. 60 illustrate cross-sectional illustrations cut along the bit line and word line directions of FIG. 58, respectively. Memory device 750 includes a substrate 12 of a first conductivity type such as p-type, for example. The memory device 750 includes a deep well 29 of the second conductivity type, such as n-type. Memory device 750 also includes a first buried layer 32 of a first conductivity type, such as p-type, for example; a second buried layer 22 of a second conductivity type, such as n-type, for example; a floating body 24 of the first conductivity type, such as p-type, for example; and source/drain 16 and 18 of the second conductivity type, such as n-type, for example. Buried layers 22 and 32 may be formed by an ion implantation process on the material of substrate 12. Alternatively, buried layer 22 and 32 and the floating body region 24 can be grown epitaxially on top of substrate 12 or formed through a solid state diffusion process. The floating body 24 of the first conductivity type is bounded on top by source 16, drain 18, and insulating layer 62 and by surface 14, on the sides perpendicular to the bit line direction by deep trench isolation 26, on the other sides perpendicular to the word line direction by shallow trench isolation 28, and on the bottom by second buried layer 22. The bottom of the deep trench isolation 26 resides below interface between the first buried layer 32 and the substrate 12, which insulates the floating body region 24, the first buried layer 32 and second buried layer 22 along the bit line direction. The bottom of the shallow trench isolation 28 is extended below the second buried layer 22 which insulates the second buried layer 22. The first buried layer 32 may be connected via recessed metal 40 as the same manner explained in FIGS. 57A-57C. While the body 24 and the second buried layer 22 are not directly connected to any terminals, the first buried layer 32 is connected to the buried layer terminal 76 according to the present invention. Deep well 29 may be continuous along both bit line and word line direction and connected to external terminal 79.

FIG. 61 illustrates a layout view of memory array 800 according to another embodiment of the present invention. The memory array 800 is located within a buried well region 170 layer. The DIFF region 130 is continuous along plurality of transistors along the I-I′ direction illustrated in FIG. 61 and thus there is no insulating layer 26 in the I-I′ direction. The memory array 800 includes additional dummy POLY layers 160D which overlays a DIFF region 130 (hence being referred to as dummy layer) and is used to electrically isolate one memory cell 850 from neighboring memory cells 850 by forming a depletion region or weak accumulation region in the DIFF region 130 under the dummy POLY layers 160D. In this case, the depletion boundary due to the dummy POLY 160D is desired to be substantially close to the depletion boundary formed by the buried layer region 22. The dummy layer 160D for example may be a result of restrictive design rules (which guides the layout drawing of the layers) for better lithography patterning process. The DIFF layers 130 define the active regions of the memory cell (regions between the insulating layers), where the layers in between the DIFF layers 130 define the insulating layers 26. The POLY layers 160 and dummy POLY layers 160D define the gate region of the memory cell 850 as shown in the cross-sectional view of FIG. 62. The POLY 160 and dummy POLY 160D may comprise the same materials, but may alternatively be formed by different materials. For example, materials with higher work function (which is defined as the minimum energy to remove an electron from a solid to a point in the vacuum immediately outside the solid surface) may be used for dummy POLY 160D. The materials for dummy POLY 160D may be the same material for the gate material being used for the p-type transistor for the logic circuit. Alternatively, the material for the dummy POLY 160D may be the specially made with its work function designed to be substantially identical to valence band edge of the silicon or other materials forming the substrate region 112.

As shown in FIG. 61, the unit cell of the memory cell 850 comprises three POLY 160 regions: two 160D to define the dummy transistor region and another 160 to define the transistor region. The overlap between POLY 160 and DIFF 130 layers form the channel region of the memory cell 850, for example the region beneath gate region 160 and dielectric layer 162, between the source line region 16 and bit line region 18 shown in FIG. 62.

Each memory cell 850 in memory array 800 is insulated from neighboring memory cells 850 by the insulating layer 26 in one direction along the word line direction, orthogonal to the I-I′ direction, and by turning off the dummy transistor in the other direction along the bit line direction. In the operations of the memory cell 850, the dummy transistor is turned off by applying about 0.0V or a negative voltage, for example about −0.2V (where the dummy transistor is n-channel transistor).

FIG. 63 schematically illustrates memory cell 850F having a fin structure according to another embodiment of the present invention. Each memory cell 850F in a memory array of memory cells 850F is insulated from neighboring memory cells 850F by the insulating layer 26 in one direction, and by turning off the dummy transistor in the other direction. In the operations of the memory cell 850F, the dummy transistor is turned off by applying about 0.0V or a negative voltage, for example about −0.2V (where the dummy transistor is n-channel transistor).

Several operations can be performed by memory cells 850 and 850F such as holding, read, write logic-1 and write logic-0 operations, and have been described in U.S. Pat. No. 9,230,651 to Widjaja et al., titled “Memory Device Having Floating Body Transistor” (“Widjaja-3”) and U.S. Pat. No. 8,077,536, “Method of Operating Semiconductor Memory Device with Floating Body Transistor Using Silicon Controlled Rectifier Principle” (“Widjaja-2”), which are both hereby incorporated herein, in their entireties, by reference thereto.

FIG. 64 illustrates an example of a standby operation performed on memory cell 850F (and similarly on memory cell 850). A standby operation can be performed by applying zero bias on the selected WL terminal 70, applying zero bias to the selected BL terminal 74, a positive bias applied to the BW terminal 76, zero bias applied to the substrate terminal 78, and zero or negative bias to the dummy WLD terminal 70D.

In one embodiment the bias conditions for the standby operation on memory cell 850F in an array of memory cells are: 0 volts is applied to selected WL terminal 70, 0 V is applied to unselected WL terminal 70, 0 volts is applied to the selected BL terminals 74, 0 volts is applied to unselected BL terminal 74, a positive voltage, for example, +1.0 volts is applied to BW terminal 76, 0 volts is applied to the substrate terminal 78, and 0 volts is applied to the dummy WLD terminal 70D. In other embodiments, different voltages may be applied to the various terminals of memory cell 850F and the exemplary voltages described are not limiting.

FIG. 65 illustrates an example of a read operation performed on memory cell 850F (and similarly on memory cell 850). A read operation can be performed by applying a positive bias on the selected WL terminal 70, applying a positive bias to the selected BL terminal 74 (less positive than the positive bias applied to the selected WL terminal 70), a positive bias applied to the BW terminal 76, zero bias applied to the substrate terminal 78, and zero or negative bias to the dummy WLD terminal 70D.

In one embodiment the bias conditions for the read operation on a selected memory cell 850F in an array of memory cells 850F are: +1.0 volts is applied to selected WL terminal 70, 0 V is applied to unselected WL terminals 70, +0.2 volts is applied to the selected BL terminals 74, 0 volts is applied to unselected BL terminals 74, 0 volts is applied to the selected SL terminal 72, 0 volts is applied to unselected SL terminals 72, a positive voltage, for example, +1.0 volts is applied to BW terminal 76, 0 volts is applied to the substrate terminal 78, and 0 volts is applied to the dummy WLD terminal 70D. In other embodiments, different voltages may be applied to the various terminals of memory cell 850F and the exemplary voltages described are not limiting.

FIG. 66 illustrates an example of a write logic-1 operation performed on memory cell 850F (and similarly on memory cell 850). The write logic-1 operation can be performed through capacitive coupling from the gate 160, source line region 16, and bit line region 18 to the floating body region 24. The operating region for the write logic-1 operation has been described for example in U.S. application Ser. No. 14/825,268, “Memory Device Comprising of an Electrically Floating Body Transistor” (“Han”), which is hereby incorporated herein, in its entireties, by reference thereto.

In one embodiment the bias conditions for a write logic-1 operation on memory cell 850F in an array of memory cells 850F are: +1.0 volts is applied to selected WL terminal 70, 0 V is applied to unselected WL terminals 70, +1.0 volts is applied to the selected BL terminals 74, 0 volts is applied to unselected BL terminals 74, 0 volts is applied to the selected SL terminal 72, 0 volts is applied to unselected SL terminals 72, a positive voltage, for example, +1.0 volts is applied to BW terminal 76, 0 volts is applied to the substrate terminal 78, and 0 volts is applied to the dummy WLD terminal 70D. In other embodiments, different voltages may be applied to the various terminals of memory cell 850F and the exemplary voltages described are not limiting.

FIG. 67 illustrates an example of a write logic-0 operation performed on memory cell 850F (and similarly on memory cell 850). The write logic-0 operation can be performed through forward biasing the p-n junction between floating body region 24 and source line region 16 and bit line region 18 and assisted by capacitive coupling from the gate 160 to the floating body region 24. The operating region for the write logic-0 operation has been described for example in U.S. application Ser. No. 14/825,268, “Memory Device Comprising of an Electrically Floating Body Transistor” (“Han”), which is hereby incorporated herein, in its entireties, by reference thereto.

In one embodiment the bias conditions for a write logic-0 operation on memory cell 850F in an array of memory cells 850F are: 0 volts is applied to selected WL terminal 70, 0 V is applied to unselected WL terminals 70, 0 volts is applied to the selected BL terminals 74, 0 volts is applied to unselected BL terminals 74, −0.5 volts is applied to the selected SL terminal 72, 0 volts is applied to the unselected SL terminals 72, a positive voltage, for example, +1.0 volts is applied to BW terminal 76, 0 volts is applied to the substrate terminal 78, and 0 volts is applied to the dummy WLD terminal 70D. In other embodiments, different voltages may be applied to the various terminals of memory cell 850F and the exemplary voltages described are not limiting.

FIG. 68 illustrates an alternative embodiment of this invention showing cross-sectional views of memory cell 850F cut along the dummy POLY layer 160D and the POLY layer 160. In this embodiment, the isolation layer 126D under dummy POLY layer 160D is shorter than the isolation layer 126 under POLY layer 160. So, the dummy POLY layer 160D covers substantial area of the fin body, particularly close to the junction boundary of the buried layer 122.

FIG. 69 illustrates another embodiment of this invention showing cross-sectional views of memory cell 850F cut along the dummy POLY layer 160D and the POLY layer 160. In this embodiment, the dummy POLY layer 160D is made with two different work function materials, with the upper region of dummy POLY layer 160D being made of a first material 160D-U and the lower region of dummy POLY layer 160D being made of a second material POLY 160D-L. The work function of the POLY 160D-U material may be the same or close to the gate material for p-type logic transistor or the conduction band edge of the silicon (or other materials forming the substrate region 112) while the work function of the lower region of POLY 160D-L material may be the same or close to the gate material for n-type logic transistor or the valence band edge of the silicon. Therefore, at zero volts at the dummy POLY layer 160D, the upper portion of the gate 160D-U can suppress the flow of electron current across the adjacent source to drain region while the lower portion of the gate 160D-L can suppress the penetration of excess holes from body of the neighboring logic-1 states.

FIGS. 70A-70B schematically illustrate a conventional gate-all-around nanowire transistor structure fabricated on bulk wafer. The source and drain regions 16/18 are anchored on the bulk substrate while the body region 124 is suspended and fully wrapped around by the gate 160.

FIGS. 71A-71B schematically illustrate cross-sectional views of memory cell 850F according to another embodiment of this invention. This embodiment may be modified from the gate-all-around fabrication process or from conventional FinFET process. Alternatively, this embodiment may be implemented by monolithically hybridizing the FinFET and gate-all-around process as the U.S. Pat. No. 8,809,957 B2 “Nanowire FET and FinFET hybrid technology”, which is hereby incorporated herein, in its entirety, by reference thereto. This embodiment features that the DIFF region is continuous along the bit line direction and thus no insulating layer such as shallow trench isolation is formed. The memory array comprising these cells 850F includes additional dummy POLY layer 160D which fully surrounds the suspended nanowire-type dummy body 124D. The suspended dummy body 124D may be fabricated by the part of the logic gate-all-around nanowire transistor fabrication. The memory array 850F also includes POLY layer 160 that covers the fin-type body of the memory cell. The fin body may be fabricated by the part of the logic FinFET transistor fabrication. The FinFET portion works as memory cell while the gate-all-around portion works for isolating the bodies of neighboring FinFET. In order to electrically isolate the bodies of neighboring FinFET cell, the junction between the buried n-well 122 and the fin body 124 are formed above the top surface of the residual silicon fin under the dummy POLY 160D.

FIG. 72 schematically illustrates a memory cell 1200 comprising an access transistor 42′ and a memory transistor 40 having different conductivity type, for example as described in U.S. application Ser. No. 14/380,770, “Memory Cell Comprising First and Second Transistors and Methods of Operating”, which is hereby incorporated herein, in its entirety, by reference thereto.

FIG. 73 schematically illustrates an example of a write operation performed on memory array 1220 of memory cells 1200 (including two exemplary instances of memory cell 1200 being labeled as 1200 a and 1200 b as shown) arranged in rows and columns. The write operation may be performed by applying the following bias conditions: a negative voltage is applied to the selected WL2 terminal 72, a positive voltage is applied to the selected WL1 terminal 70, zero voltage is applied to the selected SL terminal 74, zero or positive voltage is applied to the BW terminal 78, and zero voltage is applied to the SUB terminal 80. A positive voltage is applied to the selected BL terminal 76 for a write logic-1 operation and a negative voltage is applied to the selected BL terminal 76 for a write logic-0 operation. In FIG. 73, write logic-0 and write logic-1 operations are performed on memory cells 1200 a and 1200 b, respectively. The bias conditions applied to the memory cells 1200 a and 1200 b are illustrated in FIGS. 74A and 74B, respectively. The positive voltage applied to the selected WL1 terminal 70 may be configured to optimize write logic-0 and write logic-1 operations.

FIG. 73 also illustrates the bias condition applied to the unselected memory cells: a positive voltage is applied to the unselected WL2 terminal 72 (to turn off the access transistor 42′), zero voltage is applied to the unselected WL1 terminal 70 (to turn off the memory transistor 40), zero voltage is applied to the unselected SL terminal 74, zero voltage is applied to the unselected BL terminal 76, zero or positive voltage is applied to the BW terminal 78, and zero voltage is applied to the SUB terminal 80.

FIG. 75 schematically illustrates an exemplary waveform that can be applied to the selected WL2 terminal 72, selected BL terminals 76, and selected WL1 terminal 70. There is a time delay t_(delay) between the time the access transistor 42′ is turned on (by applying a negative voltage to the selected WL2 terminal 72) and the memory transistor 40 is turned on. Before the memory cell 40 is turned on, the access transistor 42′ will pass the voltage applied to the BL terminal 76 to the drain region 18 of the memory transistor 40. For memory cell 1200 a, a negative bias condition is now applied to the drain region 18, and the p-n junction between the floating body 24 and the drain region 18 is forward-biased, evacuating holes from the floating body 24. For memory cell 1200 b, a positive bias condition is now applied to the drain region 18. After t_(delay), the selected WL1 terminal is raised to a positive voltage. Under these bias conditions (positive voltage applied to the drain region 18 and the gate region 60), the memory cell 1200 b will be written to logic-1 state through impact ionization mechanism or through capacitive coupling mechanism. The time delay t_(delay) is configured such that the write logic-0 operation can be completed. In one particular non-limiting embodiment, the time delay t_(delay) is 100 picoseconds, but may range from 10 picoseconds to 1 microsecond.

In one particular non-limiting embodiment, about −1.2 volts is applied to the selected WL2 terminal 72, about +1.2 volts is applied to the selected WL1 terminal 70, about +1.2 volts and about −0.2 volts is applied to the selected BL terminal 76 for write logic-1 and write logic-0 operations, respectively, about +1.2 volts is applied to the selected BW terminal 78, and about 0.0 volts is applied to the SUB terminal 80. For the unselected cells, about +1.2 volts is applied to the unselected WL2 terminal 72, about 0.0 volts is applied to the unselected WL1 terminal 70, about 0.0 volts is applied to the unselected BL terminal 76, about +1.2 volts is applied to the selected BW terminal 78, and about 0.0 volts is applied to the SUB terminal 80.

From the foregoing it can be seen that a memory cell having an electrically floating body has been described. While the foregoing written description of the invention enables one of ordinary skill to make and use what is considered presently to be the best mode thereof, those of ordinary skill will understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiment, method, and examples herein. The invention should therefore not be limited by the above described embodiment, method, and examples, but by all embodiments and methods within the scope and spirit of the invention as claimed. 

1-20. (canceled)
 21. A semiconductor memory array comprising: a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein at least two of said semiconductor memory cells include: a memory transistor comprising a bi-stable floating body transistor having a first floating body region and a back-bias region configured to generate impact ionization when said memory cell is in one of first and second states, and wherein said back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of said first and second states; and an access device; wherein said access device comprises a second floating body region; wherein said bi-stable floating body transistor and said access device are electrically connected in series; and wherein said back-bias region is commonly connected to at least two of said semiconductor memory cells.
 22. The semiconductor memory array of claim 21, wherein a capacitance of said first floating body region is different from a capacitance of said second floating body region.
 23. The semiconductor memory array of claim 21, wherein said memory transistor further comprises a first gate region, and said access device further comprises a second gate region.
 24. The semiconductor memory array of claim 23, wherein a length of the first gate region is less than a length of the second gate region.
 25. The semiconductor memory array of claim 23, wherein a length of the first gate region is greater than a length of the second gate region.
 26. The semiconductor memory array of claim 21, wherein a volume of the first floating body region is smaller than a volume of the second floating body region.
 27. The semiconductor memory array of claim 23, wherein a capacitance of the first gate region is different from a capacitance of the second gate region.
 28. The semiconductor memory array of claim 21, further comprising at least one dummy gate region between said memory transistor and said access device.
 29. The semiconductor memory array of claim 28, wherein said memory transistor comprises a first gate region; and wherein a work function of said dummy gate region is higher than a work function of said first gate region.
 30. The semiconductor memory array of claim 21, wherein said semiconductor memory cell is a multi-port memory cell.
 31. The semiconductor memory array of claim 21 comprising a fin structure.
 32. A semiconductor memory array comprising: a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein at least two of said semiconductor memory cells include: a first transistor having a first floating body; a second transistor having a second floating body; a buried layer underlying both of said first and second floating bodies; a first source line region contacting said first floating body; a first drain region separated from said first source line region and contacting said first floating body; a first gate insulated from said first floating body; an insulating member insulating said first floating body from said second floating body; a second source line region contacting said second floating body; a second drain region separated from said second source line region and contacting said second floating body; and a second gate insulated from said second floating body; wherein said first drain region is electrically connected to said second source line region; wherein a capacitance of said first floating body is different from a capacitance of said second floating body; and wherein said back-bias region is commonly connected to at least two of said semiconductor memory cells.
 33. The semiconductor memory array of claim 32, wherein a volume of said first floating body is less than a volume of said second floating body.
 34. The semiconductor memory array of claim 32, wherein a length of said first gate is less than a length of said second gate.
 35. The semiconductor memory array of claim 32, wherein a length of said first gate is greater than a length of said second gate.
 36. The semiconductor memory array of claim 32, further comprising at least one dummy gate region between said first transistor and said second transistor.
 37. The semiconductor memory array of claim 36, wherein a work function of said dummy gate region is greater than a work function of said first gate.
 38. The semiconductor memory array of claim 32, wherein said first transistor and said second transistor have the same conductivity type.
 39. The semiconductor memory array of claim 32, wherein said semiconductor memory cell is a multi-port memory cell.
 40. The semiconductor memory array of claim 32 comprising a fin structure. 